1. Field of the Invention
The present invention relates to the field of integrated circuits and more particularly to timing verification and functional analysis.
2. Description of the Related Art
Known integrated circuit chips contain a large number of transistors and interconnections. Given the large number of devices and ever increasing integrated circuit chip operating frequency, full chip functional verification and full chip timing analysis presents a challenge when designing the integrated circuit chip.
FIG. 1, labeled prior art, shows a block diagram representation of a functional path. The path starts with a register 110 and ends with a register 112. Between the two gates is a functional representation 120 that performs a function on signals passing from the first gate to the second gate. A functional verification confirms that the actual behavior of an integrated circuit design conforms to an integrated circuit chip design specification.
FIG. 2, labeled prior art, shows a block diagram representation of a timing path within an integrated circuit design. The path starts with a register 210 and ends with a register 212. Between the two gates is a timing representation 220 that simulates the timing of the path. Each timing path simulation also includes a resistor capacitor input representation 222 and a resistor capacitor output representation 224 at the input and the output of the timing representation 220. When designing an integrated circuit chip, it becomes important to verify the timing of every path within the chip. The propagation delay of each path should be less than a predefined cycle time.
This design issue becomes even more challenging with the large number of multicycle paths and the process involved in verification of multicycle paths. A single incorrect definition in the timing definition might result in a false timing analysis. The concept of making a path multicycle in high-frequency designs is known. A path is multicycle if the source holds the data valid for n (>1) clock cycles and the destination latches/uses the data at the end nth cycle. Due to the trend of shrinking device sizes, increasing the number of devices on an integrated circuit chip die, increasing the integrated circuit chip die sizes, smaller cycle times and increasing interconnect-delay to gate-delay ratio, multicycle paths present an attractive design choice. This design choice may be especially attractive for interconnect or megacell dominated paths. However, multicycle paths present associated functional simulation and timing verification challenges. Any destination using multicycle path data before the end of an nth cycle can result in a malfunction indication. For this reason, rtl monitors may be placed to verify that data is not used before the nth cycle. Also, multicycle paths should be properly accounted for during static timing analysis to filter out false violations and more importantly to prevent these false violations from masking actual timing violations.
Accordingly, it is important when performing functional simulation and timing verification to ensure the accuracy of functional definitions, the accuracy of multicycle timing definitions and the consistency between functional definitions and timing definitions for a particular integrated circuit chip design.